EDN

10.22.98 Covering your HDL chip-design bets

Code-coverage increases simulation time. The added time depends on code quality, coding style, the extensiveness of the coverage feature set, and the simulator interface. The increased use of imported ...
Business Wire

Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a customizable tool qualification data ...
EDN

Automating rule sets for safety-critical HDL coding

During the development process for safety-critical designs, all precautions should be taken to prevent device failures from all foreseeable sources, including those due to poor design methods and ...
Electronic Design

New App From The Mathworks Generates HDL Code From System Models

[September 18, 2006] The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...